Abstract

This paper addresses the multi-frequency clock synthesis issue in Beidou Generation II RF chips, proposing a clock synthesis solution based on fractional frequency division technology. This solution can unify various external input clocks into the required 16.368 MHz system clock and is implemented using hardware description language (HDL). The design has been validated through silicon testing, demonstrating a simple structure and suitability for ASIC implementation.

Introduction

Satellite navigation RF chips must be compatible with multiple external clock frequencies to work with shared oscillators used in devices like mobile phones. The frequency of the Beidou Generation II B1 signal is 1561.098 MHz, which must be down-converted to a fixed intermediate frequency (IF). This paper focuses on the methodology for converting different input clock frequencies into the system-required 16.368 MHz clock, especially when the frequency becomes a non-integer multiple after frequency multiplication.

Circuit Principles and Implementation

The multi-frequency clock synthesis circuit adopts an accumulator and dual-counter structure, using alternating work of two frequency dividers to achieve fractional frequency division. When the fractional part of the target frequency is close to 0.25 or 0.75, a half-pulse width shifting technique is applied to optimize the output performance. The entire design is implemented in Verilog HDL to ensure that it is process-independent.

Performance Analysis

By performing 40x frequency multiplication and division on a 26 MHz input clock, a 16.368 MHz output clock was successfully generated. Test results showed a peak jitter of 480.3 ps and a frequency deviation of less than 1 ppm, meeting the design requirements. This solution is also effective for other common input frequencies, with all performance metrics meeting the RF chip application requirements.

Conclusion

The proposed multi-frequency clock synthesis solution has been successfully applied in the SDT6112 Beidou Generation II RF chip. Practical tests show that the design is stable and simple, particularly suitable for ASIC implementation. It holds great potential for applications in communication and specialized DSP (Digital Signal Processing) fields.