RF chips, as the core component of modern wireless communication and navigation systems, directly influence the accuracy, stability, and integration level of the entire system. In GNSS (Global Navigation Satellite System) RF frontends, frequency synthesizers are key modules responsible for generating local oscillator signals, and fractional frequency division technology is essential for achieving high-precision and low spurious frequency synthesis. This paper focuses on the fractional frequency division problem in RF chips, analyzing two mainstream modulator structures and exploring their application advantages and development prospects in multi-mode navigation systems.

1. Background of RF Chips and Fractional Frequency Division Technology

In GNSS receivers, RF chips amplify, filter, and down-convert the weak satellite signals received by the antenna. The local oscillator signal required for down-conversion is generated by a phase-locked loop (PLL) frequency synthesizer, where the output frequency fof_ofo​ and reference frequency freff_{ref}fref​ satisfy:

fo=N.F×freff_o = N.F \times f_{ref}fo​=N.F×fref​

where N.FN.FN.F is the total division ratio, usually non-integer. Traditional integer frequency division cannot meet the needs of multi-frequency and high-precision local oscillators, leading to the emergence of fractional frequency division technology. However, fractional frequency division introduces “fractional spurious,” and if the spurious frequencies fall within the loop bandwidth, they cannot be filtered out, seriously affecting the RF chip’s output spectrum purity and system performance.

2. Two Typical Structures of Fractional Frequency Division Modulators

Accumulator Structure Modulator

The accumulator structure is an early commonly used method for fractional frequency division. By cascading multi-stage accumulators, the division ratio can switch between NNN and N+1N+1N+1, achieving statistical averaging fractional frequency division. This structure is simple and easy to implement but generates concentrated low-frequency spurious, which limits its application in high-end RF chips due to higher spurious power.

MASH1-1-1 Δ-Σ Structure Modulator

The MASH (Multi-stage Noise SHaping) structure uses multiple first-order Δ-Σ modulators in cascade to achieve high-pass shaping of quantization noise. For MASH1-1-1, its transfer function is:

y(z)=z−3⋅x(z)+(1−z−3)⋅e3(z)y(z) = z^{-3} \cdot x(z) + (1 – z^{-3}) \cdot e_3(z)y(z)=z−3⋅x(z)+(1−z−3)⋅e3​(z)

This structure pushes the error signal e3(z)e_3(z)e3​(z) to higher frequencies, resulting in a cleaner output spectrum at lower frequencies. Moreover, it has a wider output control word range (e.g., from -7 to 7), allowing the division ratio to randomly jump between multiple values, further dispersing spurious energy and significantly improving in-band phase noise and spurious performance.

3. Performance Simulation and Comparative Analysis

For typical GNSS system scenarios with GPS L1 and BD-2 B1 frequencies, using an intermediate frequency of 3.996 MHz and a reference frequency of 16.368 MHz, the two structures were simulated using ADS. The results show:

The accumulator structure has significant spurious peaks in the 0-2 MHz range, affecting PLL in-band performance.

The MASH1-1-1 structure, by noise shaping, pushes spurious energy to higher frequencies (e.g., >2 MHz), significantly improving suppression of spurious in the critical low-frequency range.

Since the PLL loop bandwidth is typically 1/10th of the reference frequency (about 1.6 MHz), high-frequency spurious can be effectively filtered by the loop filter. Therefore, the MASH structure is better suited for high-precision GNSS RF chips in frequency synthesizers.

4. Development Trends of Fractional Frequency Division Technology in RF Chips

As navigation systems evolve towards multi-mode (BeiDou/GPS/Galileo/GLONASS), multi-frequency, and high-precision applications, the performance of frequency synthesizers in RF chips is increasingly demanding. The future development of fractional frequency division technology will focus on:

High-Order Δ-Σ Modulators: Further enhancing noise shaping efficiency and reducing in-band phase noise.

Fully Digital PLL (ADPLL) Integration: Achieving more flexible modulator structures and calibration mechanisms in RF chips.

Anti-Process Fluctuation Design: Ensuring modulator performance consistency under nanometer processes.

Multi-Frequency Rapid Switching: Supporting dynamic division ratio configurations to meet cognitive navigation and anti-jamming requirements.

5. Conclusion

Fractional frequency division technology is a key link in enhancing the spectrum performance and system integration of RF chips. While the accumulator structure is simple and easy to use, its spurious performance is limited. In contrast, the MASH1-1-1 Δ-Σ structure, with its excellent noise shaping capabilities, is more suitable for frequency synthesizers in high-performance GNSS RF chips. With advances in technology and algorithm optimization, fractional frequency division technology will continue to drive RF chips toward lower power consumption, higher precision, and stronger anti-jamming capabilities, providing solid support for next-generation navigation and communication systems.