Optimizing RF Chips for BeiDou-3: Σ-Δ Modulator Design and Performance Enhancement

Jason Chen     October 4, 2025 

Abstract

With the full implementation of the BeiDou-3 global satellite navigation system, the performance of RF chips has become crucial for ensuring the system’s positioning accuracy and reliability. This paper delves into the role and optimized design of the Σ-Δ modulator in the BeiDou-3 RF chip, focusing on mitigating fractional spurs in the phase-locked loop (PLL) frequency synthesizer and enhancing overall system performance.

I. Technical Challenges and Solutions of Fractional Dividers in RF Chips

In the BeiDou-3 RF chip, the phase-locked loop frequency synthesizer is responsible for generating the local oscillator signal. Since the carrier frequencies in the BeiDou system are non-integer multiples of the reference frequency, fractional dividers are essential. However, traditional fractional dividers produce fractional spurs, which degrade the purity of the output spectrum.

To address this issue, Σ-Δ modulation technology is employed. This technique transforms fractional spurs into quantization noise and applies noise shaping techniques to move these spurs to higher frequencies. The PLL’s low-pass characteristics then filter them out, significantly improving system performance.

II. Optimized Design of a MASH 1-1-1 Σ-Δ Modulator for RF Chips

The study focuses on a MASH 1-1-1 Σ-Δ modulator, which ensures effective noise shaping while avoiding the complexity and resource consumption of higher-order modulators. However, for certain fractional input values, the modulator shows structural parasitics, manifesting as spurious spectral lines in the output spectrum.

Through detailed analysis, the occurrence of these parasitics is linked to the input value’s parity. When the input is even, periodicity in the modulator output sequence results in spectral peaks in the high-frequency region, particularly with an input value of 0.25.

III. Innovative Dither Circuit Design for RF Chip Optimization

To mitigate structural parasitics, a specially designed dither circuit was introduced. By injecting a pseudo-random sequence into the modulator, the periodicity of the output sequence is disrupted. Traditional dither injection methods introduce additional in-band noise, but this study introduces an improved mapping scheme to reduce noise:

New Mapping Scheme: The traditional binary mapping (-1, 1) is expanded to a four-value mapping (-2, -1, 0, 1), allowing more precise dither control.

Shaping Processing Optimization: A first-order noise shaping function is applied to the dither signal, effectively reducing in-band noise while optimizing resource usage.

Simulation results show that this improved dither method significantly reduces structural parasitics while maintaining low in-band noise, even for fractional input values like 0.1251, 0.6265, 0.5014, and 0.2511.

IV. Circuit Implementation and Performance Verification

The study involved designing a complete MASH 1-1-1 modulator logic circuit. This includes a three-stage cascaded accumulator and dedicated noise shaping circuitry, optimized for the BeiDou-3 RF chip‘s specific frequency bands (B11, B2a, B2b, and B3). Behavioral simulations using Modelsim software demonstrated excellent performance across all test cases, confirming:

Effective suppression of fractional spurs

Improved output spectrum smoothness

Enhanced system phase noise performance

V. Technical Value and Application Prospects of RF Chips

The optimized Σ-Δ modulator design addresses the technical challenges associated with fractional frequency division in the BeiDou-3 RF chip. Key innovations include:

Structural optimization to suppress modulator parasitics

A novel mapping method for improved dither control

A balance between performance and resource consumption

This RF chip design not only supports BeiDou-3 but also holds significant promise for other global navigation satellite systems. As navigation applications expand, these advancements will support critical sectors such as autonomous driving, precision agriculture, and emergency communications.

VI. Conclusion

The RF chip design for BeiDou-3 using an optimized Σ-Δ modulator enhances the chip’s performance, offering a solution to fractional spurs and improving overall system reliability. With the continued advancement of RF chips for satellite navigation, these technologies are paving the way for more accurate, efficient, and scalable global navigation systems.

Jason Chen

Dr. Jason Chen – Post-Silicon Validation & Automation Expert Dr. Jason Chen is a seasoned expert in semiconductor test, specializing in developing advanced automated test solutions for mixed-signal, analog discrete, MCU, and SoC applications. He brings years of extensive experience from leading instrument manufacturers, encompassing application solution development, lab characterization automation, production ramp-up, and test platform migration. Dr. Chen possesses a deep understanding of the critical role post-silicon validation plays in ensuring high-quality chip manufacturing. This comprehensive process includes bring-up, performance validation, robustness testing, characterization, ATE NPI, and reliability testing. He is dedicated to advancing post-silicon validation methodologies by fostering…

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