Design and Implementation of T/R Component Systems Based on W-Band SOC RF Chips
Jason Chen October 14, 2025
With the widespread application of millimeter-wave technology in fields such as collision avoidance radar, automotive electronics, and rail transportation, the W-band (75–110 GHz) has gradually become the ideal frequency band for short-range radar systems due to its high bandwidth, high resolution, and ease of integration. As the core of the transceiver component, the performance of the RF chip directly determines the detection capability and reliability of the entire radar system. This article focuses on the design of the T/R component system based on W-band SOC RF chips, providing a comprehensive discussion from chip selection, system architecture design, to the simulation and implementation of key RF interconnection structures.
1. Development of W-Band RF Chips and System Integration Advantages
In recent years, both domestic and international markets have made significant progress in the development of multi-channel, high-integration W-band RF chips. For example, Gatlian Microelectronics released a 77 GHz CMOS RF chip that realizes “2 transmitters, 4 receivers” with high-density integration, greatly promoting the miniaturization and cost reduction of vehicle radar systems. These RF chips integrate key modules such as low-noise amplifiers, power amplifiers, mixers, phase-locked loops, and phase shifters, offering high gain, low noise, and fast switching capabilities, laying a solid foundation for the system-level packaging of T/R components.
Compared to traditional systems built with discrete components, the use of SOC RF chips not only significantly reduces system size but also decreases system complexity and power consumption, improving overall reliability and production efficiency.
2. T/R Component System Architecture and RF Link Design
The T/R component designed in this paper adopts a “2T4R” architecture and operates in the 75–80 GHz frequency range, with FMCW modulation capabilities. The system uses a highly integrated SOC RF chip as the core, with surrounding components including multi-layer PCBs, waveguide interfaces, power management, and control circuits to achieve complete transceiver functionality.
In the receiver chain, weak signals received by the antenna are input through a waveguide-microstrip probe structure, amplified by a low-noise amplifier, mixed with the local oscillator signal, and down-converted to baseband. After filtering and gain control, the signal is output. The transmission chain reverses this process, converting the baseband signal to a higher frequency and amplifying it before radiation through the antenna. Key parameters such as noise figure, gain, and linearity of the entire chain are verified and optimized through system simulations.
3. Design and Simulation of Key RF Interconnection Structures
To achieve efficient transmission of high-frequency signals within multi-layer PCBs, this paper focuses on the design of three types of RF interconnection structures:
Waveguide-Microstrip Probe Transition: Addressing the issue of high-frequency loss in the W-band, a fine needle-shaped electromagnetic coupling probe structure was proposed, with a short-circuit surface integrated within the PCB. Simulation results show that the insertion loss in the 72.3–82.5 GHz range is below 0.2 dB, with an excellent return loss of better than -20 dB, demonstrating good broadband characteristics and manufacturing tolerance.
Vertical Transition Structure: A “GCPW-coaxial-GCPW” vertical interconnection scheme was adopted to effectively suppress electromagnetic leakage and mode distortion at high frequencies. This structure maintains a return loss better than -16 dB across the entire passband below 100 GHz, with insertion loss of only 0.42 dB at 40 GHz, making it suitable for high-density system integration.
BGA to Microstrip Transition Structure: For RF chip BGA packaging, a GCPW to microstrip line structure with matching circuits was designed, successfully counteracting parasitic capacitance introduced by the solder balls. In the 72–106 GHz range, the return loss is better than -15 dB, with a target frequency range below -20 dB and insertion loss of 0.4 dB.
4. System Simulation and Performance Verification
System-level simulations of the entire transceiver link were performed using ADS software. The receiver channel, within the 75–80 GHz band, showed a noise figure of 11.324 dB and a gain of 57.602 dB, ensuring pure baseband output signals. The transmission channel achieved a gain of 24.602 dB, with output power exceeding 5 dBm, meeting the system requirements. The simulation results confirm the feasibility and superiority of the designed RF chip and its interconnection structures in high-frequency systems.
5. Summary and Outlook
Based on W-band SOC RF chips, this article successfully designs and simulates a high-performance, miniaturized T/R component system. By optimizing key structures such as the waveguide probe, vertical transitions, and BGA interconnections, the system achieves low loss, wide bandwidth, and high integration. In the future, with the further maturity of RF chip processes and continuous innovation in packaging technologies, W-band T/R components will play a more important role in fields such as autonomous driving, intelligent transportation, and drone navigation.
Jason Chen
Dr. Jason Chen – Post-Silicon Validation & Automation Expert Dr. Jason Chen is a seasoned expert in semiconductor test, specializing in developing advanced automated test solutions for mixed-signal, analog discrete, MCU, and SoC applications. He brings years of extensive experience from leading instrument manufacturers, encompassing application solution development, lab characterization automation, production ramp-up, and test platform migration. Dr. Chen possesses a deep understanding of the critical role post-silicon validation plays in ensuring high-quality chip manufacturing. This comprehensive process includes bring-up, performance validation, robustness testing, characterization, ATE NPI, and reliability testing. He is dedicated to advancing post-silicon validation methodologies by fostering…
