Currently, satellite navigation chips mainly include components such as GNSS RF receivers, GNSS baseband signal processors, microprocessors, power management, memory and control units, storage devices, serial devices, and peripheral interface circuits. Due to the complexity of chip design, especially the integration of RF and baseband in SoC chips, the ability to design satellite navigation chips directly impacts their performance, sensitivity, power consumption, size, and cost. This, in turn, greatly affects the competitiveness of navigation and positioning terminal products. Therefore, the direction of development for satellite navigation chips largely represents the trends of satellite navigation terminal products. From the structure of satellite navigation chips, it is clear that integration, performance, and power consumption will be the key technological challenges for Beidou chip development in the future.

Chip Technology Development Directions

1. Suitable Process and SoC Integration Design to Improve Chip Integration
Currently, the most mature and cost-effective process for navigation and positioning chips is the 40nm CMOS process, which provides advantages such as low power consumption, low cost, and low risk. In the future, this will evolve toward a 22nm CMOS process.
SoC (System on Chip) integrates the microprocessor, analog IP cores, digital IP cores, memory, and peripheral interfaces into a single chip, offering high integration, strong functionality, low power consumption, and small size. This significantly reduces the development costs and time of electronic/information system products, shortens development cycles, and improves the competitiveness of products. The development of SoC chips is a natural trend in chip technology.

2. Chip-Level Dual-Frequency Joint Positioning to Improve Positioning Accuracy
Dual-frequency positioning greatly enhances positioning accuracy and reliability in complex urban environments. The main factors affecting satellite positioning accuracy include ionospheric delay and the multipath effects caused by building and obstacle reflections. In general, higher bandwidth and higher code rates lead to less interference from refraction and reflection.
Dual-frequency and multi-frequency joint positioning technologies are already validated methods for improving positioning accuracy and resistance to multipath effects. However, these functions are typically achieved through boards or FPGA (Field Programmable Gate Array), leading to high costs, high power consumption, and large sizes. This makes it challenging for applications in smartphones, smart wearables, and other areas where low power consumption and small size are critical. The development of dual-frequency SoC single-chip technology addresses this issue and is a key international trend for the large-scale application of dual-frequency positioning.

3. Ultra-Low Power Design to Extend Standby Time
To reduce power consumption, mainstream satellite navigation chip manufacturers typically adopt dynamic voltage and frequency adjustment technology, ultra-low standby power design techniques, and embedded memory technologies. Currently, the standby power consumption of mainstream satellite navigation chips is less than 2uA, achieving the same standby performance as low-power MCU (Microcontroller Unit) chips.
Furthermore, the use of “embedded memory processes” in satellite navigation chips, which integrate parallel interface memory units, reduces packaging costs and improves the processor’s efficiency in accessing memory, thus lowering the power consumption of memory access.

Beidou High-Precision Mass Market Applications

With the rapid development of smartphones, the Internet of Things (IoT), connected vehicles, drones, and other applications, the demand for precise location services has become increasingly widespread. The positioning accuracy required by various mass-market positioning terminals has reached “meter-level” or even “sub-meter level.” The limitations of traditional high-precision large-sized, high-power consumption boards are becoming more evident and can no longer meet the needs of high-precision mass-market applications. Chip-level high-precision positioning products are the inevitable trend and result of high-precision mass-market applications.

Some industry application markets, the civilian market, and IoT markets mainly target handheld terminals, portable mobile devices, and wearable devices. Chip-level high-precision solutions, with their inherent advantages of ultra-low power consumption and long standby time, will greatly enhance the competitiveness of high-precision terminal products. This will be the primary market for Beidou chips.