RFchips are core components in wireless systems such as satellite navigation and mobile communications. The performance of RFchips directly impacts the stability and accuracy of the entire communication link. In GNSS (Global Navigation Satellite System) RFchips, fractional divider circuits play a crucial role in frequency synthesis, helping to suppress spurious signals and improve signal quality. This article, based on a technical paper, systematically introduces the design methods and performance optimization strategies for fractional dividers aimed at RFchips in GNSS applications.

1. Technical Background of RFchips and Fractional Dividers

In GNSS receivers, RFchips are responsible for receiving high-frequency signals from satellites and down-converting them to intermediate frequencies for further processing. The generation of local oscillator signals relies on a phase-locked loop (PLL) frequency synthesizer, where fractional dividers serve as the core for flexible frequency configuration. Traditional integer division methods cannot meet the needs of multi-frequency and high-precision applications, making fractional division technology a key focus in modern RFchips design.

2. Design and Implementation of Fractional Divider Circuits

This study presents a fractional divider circuit designed for GNSS RFchips, which supports arbitrary fractional division ratios within the range of 16 to 255. The circuit uses a MASH1-1-1 structure Sigma-delta modulator, employing noise-shaping technology to push quantization noise to higher frequencies. This noise is then filtered out by the loop filter, effectively suppressing fractional spurious signals.

Moreover, to address the parasitic issues in the modulator when inputting specific even values (e.g., 0.25, 0.5), the research team introduced a jitter circuit based on a deformed m-sequence before the modulator. This circuit injects a pseudo-random sequence with a mean of zero, disrupting the periodicity of the modulator output, thereby eliminating spurious signals at fixed frequencies.

3. Simulation Validation and Performance Analysis

To validate the circuit performance, the research team conducted modeling and simulation using ADS software. The simulation results show that when typical GNSS frequencies (e.g., GPS L1 frequency at 1575.42 MHz) and different external reference frequencies (13 MHz, 16.35 MHz, 24.55 MHz) are input, the modulator output spectrum becomes smooth with no visible glitches. The average value remains unchanged, confirming the circuit’s effectiveness in eliminating spurious signals.

Further functional simulations were performed in Modelsim using Verilog HDL. The simulation results demonstrate that the divider’s output is accurate and that the average value aligns with the target fractional division ratio, verifying the correct functionality of the circuit.

4. Comprehensive Performance Improvement of RFchips

The successful design of this fractional divider circuit not only enhances the frequency flexibility and accuracy of GNSS RFchips but also significantly improves the spectral purity of the output signal. By optimizing the Sigma-delta modulator structure and introducing an intelligent jitter mechanism, the circuit excels in suppressing spurious signals and reducing phase noise, providing reliable front-end support for high-precision navigation and positioning.

5. Conclusion and Future Outlook

The proposed fractional divider circuit combines high integration and low spurious characteristics, making it particularly suitable for GNSS RFchips that require high-frequency purity. With the rapid development of 5G, IoT, and BeiDou (the Chinese satellite navigation system), RFchips are evolving toward multi-band, low-power, and high-linearity designs. In the future, with the integration of more advanced manufacturing processes and algorithm optimizations, fractional division technology is expected to play a key role in more high-frequency, high-sensitivity RFchips, helping domestic RFchips gain a more prominent position in the global market.