{"id":1301,"date":"2025-10-05T15:32:27","date_gmt":"2025-10-05T15:32:27","guid":{"rendered":"https:\/\/www.wallisemi.com\/?p=1301"},"modified":"2025-10-06T15:34:50","modified_gmt":"2025-10-06T15:34:50","slug":"nghien-cuu-ve-tong-hop-dong-ho-da-tan-so-trong-cac-chip-rf-cua-he-thong-beidou-the-he-ii","status":"publish","type":"post","link":"https:\/\/www.wallisemi.com\/vi\/blog\/industry-insights\/research-on-multi-frequency-clock-synthesis-in-beidou-generation-ii-rf-chips\/","title":{"rendered":"Nghi\u00ean c\u1ee9u v\u1ec1 t\u1ed5ng h\u1ee3p \u0111\u1ed3ng h\u1ed3 \u0111a t\u1ea7n s\u1ed1 trong chip RF th\u1ebf h\u1ec7 II c\u1ee7a h\u1ec7 th\u1ed1ng Beidou"},"content":{"rendered":"<h4 class=\"wp-block-heading\"><strong>T\u00f3m t\u1eaft<\/strong><strong><\/strong><\/h4>\n\n\n\n<p>B\u00e0i b\u00e1o n\u00e0y \u0111\u1ec1 c\u1eadp \u0111\u1ebfn v\u1ea5n \u0111\u1ec1 t\u1ed5ng h\u1ee3p \u0111\u1ed3ng h\u1ed3 \u0111a t\u1ea7n s\u1ed1 trong c\u00e1c chip RF Beidou Th\u1ebf h\u1ec7 II, \u0111\u1ed3ng th\u1eddi \u0111\u1ec1 xu\u1ea5t m\u1ed9t gi\u1ea3i ph\u00e1p t\u1ed5ng h\u1ee3p \u0111\u1ed3ng h\u1ed3 d\u1ef1a tr\u00ean c\u00f4ng ngh\u1ec7 chia t\u1ea7n s\u1ed1 ph\u00e2n s\u1ed1. Gi\u1ea3i ph\u00e1p n\u00e0y c\u00f3 th\u1ec3 h\u1ee3p nh\u1ea5t c\u00e1c \u0111\u1ed3ng h\u1ed3 \u0111\u1ea7u v\u00e0o b\u00ean ngo\u00e0i kh\u00e1c nhau th\u00e0nh \u0111\u1ed3ng h\u1ed3 h\u1ec7 th\u1ed1ng 16,368 MHz theo y\u00eau c\u1ea7u v\u00e0 \u0111\u01b0\u1ee3c tri\u1ec3n khai b\u1eb1ng ng\u00f4n ng\u1eef m\u00f4 t\u1ea3 ph\u1ea7n c\u1ee9ng (HDL). Thi\u1ebft k\u1ebf \u0111\u00e3 \u0111\u01b0\u1ee3c x\u00e1c nh\u1eadn th\u00f4ng qua th\u1eed nghi\u1ec7m tr\u00ean chip, ch\u1ee9ng minh c\u1ea5u tr\u00fac \u0111\u01a1n gi\u1ea3n v\u00e0 t\u00ednh ph\u00f9 h\u1ee3p \u0111\u1ec3 tri\u1ec3n khai tr\u00ean ASIC.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Gi\u1edbi thi\u1ec7u<\/strong><strong><\/strong><\/h4>\n\n\n\n<p>C\u00e1c chip RF \u0111\u1ecbnh v\u1ecb v\u1ec7 tinh ph\u1ea3i t\u01b0\u01a1ng th\u00edch v\u1edbi nhi\u1ec1u t\u1ea7n s\u1ed1 \u0111\u1ed3ng h\u1ed3 b\u00ean ngo\u00e0i \u0111\u1ec3 c\u00f3 th\u1ec3 ho\u1ea1t \u0111\u1ed9ng v\u1edbi c\u00e1c b\u1ed9 dao \u0111\u1ed9ng chung \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng trong c\u00e1c thi\u1ebft b\u1ecb nh\u01b0 \u0111i\u1ec7n tho\u1ea1i di \u0111\u1ed9ng. T\u1ea7n s\u1ed1 c\u1ee7a t\u00edn hi\u1ec7u Beidou Th\u1ebf h\u1ec7 II B1 l\u00e0 1561,098 MHz, c\u1ea7n \u0111\u01b0\u1ee3c chuy\u1ec3n \u0111\u1ed5i xu\u1ed1ng th\u00e0nh t\u1ea7n s\u1ed1 trung gian (IF) c\u1ed1 \u0111\u1ecbnh. B\u00e0i b\u00e1o n\u00e0y t\u1eadp trung v\u00e0o ph\u01b0\u01a1ng ph\u00e1p chuy\u1ec3n \u0111\u1ed5i c\u00e1c t\u1ea7n s\u1ed1 \u0111\u1ed3ng h\u1ed3 \u0111\u1ea7u v\u00e0o kh\u00e1c nhau th\u00e0nh t\u1ea7n s\u1ed1 \u0111\u1ed3ng h\u1ed3 16,368 MHz theo y\u00eau c\u1ea7u c\u1ee7a h\u1ec7 th\u1ed1ng, \u0111\u1eb7c bi\u1ec7t khi t\u1ea7n s\u1ed1 tr\u1edf th\u00e0nh b\u1ed9i s\u1ed1 kh\u00f4ng nguy\u00ean sau khi nh\u00e2n t\u1ea7n s\u1ed1.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Nguy\u00ean l\u00fd v\u00e0 \u1ee9ng d\u1ee5ng m\u1ea1ch \u0111i\u1ec7n<\/strong><strong><\/strong><\/h4>\n\n\n\n<p>M\u1ea1ch t\u1ed5ng h\u1ee3p \u0111\u1ed3ng h\u1ed3 \u0111a t\u1ea7n s\u1ed1 \u00e1p d\u1ee5ng c\u1ea5u tr\u00fac b\u1ed9 t\u00edch l\u0169y v\u00e0 b\u1ed9 \u0111\u1ebfm k\u00e9p, s\u1eed d\u1ee5ng c\u01a1 ch\u1ebf ho\u1ea1t \u0111\u1ed9ng xen k\u1ebd c\u1ee7a hai b\u1ed9 chia t\u1ea7n s\u1ed1 \u0111\u1ec3 th\u1ef1c hi\u1ec7n chia t\u1ea7n s\u1ed1 theo t\u1ef7 l\u1ec7 ph\u00e2n s\u1ed1. Khi ph\u1ea7n ph\u00e2n s\u1ed1 c\u1ee7a t\u1ea7n s\u1ed1 m\u1ee5c ti\u00eau g\u1ea7n b\u1eb1ng 0,25 ho\u1eb7c 0,75, k\u1ef9 thu\u1eadt d\u1ecbch chuy\u1ec3n n\u1eeda \u0111\u1ed9 r\u1ed9ng xung \u0111\u01b0\u1ee3c \u00e1p d\u1ee5ng \u0111\u1ec3 t\u1ed1i \u01b0u h\u00f3a hi\u1ec7u su\u1ea5t \u0111\u1ea7u ra. To\u00e0n b\u1ed9 thi\u1ebft k\u1ebf \u0111\u01b0\u1ee3c tri\u1ec3n khai b\u1eb1ng ng\u00f4n ng\u1eef Verilog HDL \u0111\u1ec3 \u0111\u1ea3m b\u1ea3o t\u00ednh \u0111\u1ed9c l\u1eadp v\u1edbi quy tr\u00ecnh s\u1ea3n xu\u1ea5t.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Ph\u00e2n t\u00edch hi\u1ec7u su\u1ea5t<\/strong><strong><\/strong><\/h4>\n\n\n\n<p>B\u1eb1ng c\u00e1ch th\u1ef1c hi\u1ec7n nh\u00e2n v\u00e0 chia t\u1ea7n s\u1ed1 40 l\u1ea7n tr\u00ean t\u00edn hi\u1ec7u \u0111\u1ed3ng h\u1ed3 \u0111\u1ea7u v\u00e0o 26 MHz, \u0111\u00e3 t\u1ea1o ra th\u00e0nh c\u00f4ng t\u00edn hi\u1ec7u \u0111\u1ed3ng h\u1ed3 \u0111\u1ea7u ra 16,368 MHz. K\u1ebft qu\u1ea3 th\u1eed nghi\u1ec7m cho th\u1ea5y \u0111\u1ed9 dao \u0111\u1ed9ng \u0111\u1ec9nh l\u00e0 480,3 ps v\u00e0 \u0111\u1ed9 l\u1ec7ch t\u1ea7n s\u1ed1 d\u01b0\u1edbi 1 ppm, \u0111\u00e1p \u1ee9ng c\u00e1c y\u00eau c\u1ea7u thi\u1ebft k\u1ebf. Gi\u1ea3i ph\u00e1p n\u00e0y c\u0169ng hi\u1ec7u qu\u1ea3 \u0111\u1ed1i v\u1edbi c\u00e1c t\u1ea7n s\u1ed1 \u0111\u1ea7u v\u00e0o ph\u1ed5 bi\u1ebfn kh\u00e1c, v\u1edbi t\u1ea5t c\u1ea3 c\u00e1c ch\u1ec9 s\u1ed1 hi\u1ec7u su\u1ea5t \u0111\u1ec1u \u0111\u00e1p \u1ee9ng c\u00e1c y\u00eau c\u1ea7u \u1ee9ng d\u1ee5ng c\u1ee7a chip RF.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>K\u1ebft lu\u1eadn<\/strong><strong><\/strong><\/h4>\n\n\n\n<p>Gi\u1ea3i ph\u00e1p t\u1ed5ng h\u1ee3p \u0111\u1ed3ng h\u1ed3 \u0111a t\u1ea7n s\u1ed1 \u0111\u01b0\u1ee3c \u0111\u1ec1 xu\u1ea5t \u0111\u00e3 \u0111\u01b0\u1ee3c \u00e1p d\u1ee5ng th\u00e0nh c\u00f4ng trong chip RF SDT6112 thu\u1ed9c h\u1ec7 th\u1ed1ng Beidou th\u1ebf h\u1ec7 II. C\u00e1c th\u1eed nghi\u1ec7m th\u1ef1c t\u1ebf cho th\u1ea5y thi\u1ebft k\u1ebf n\u00e0y \u1ed5n \u0111\u1ecbnh v\u00e0 \u0111\u01a1n gi\u1ea3n, \u0111\u1eb7c bi\u1ec7t ph\u00f9 h\u1ee3p \u0111\u1ec3 tri\u1ec3n khai tr\u00ean ASIC. Gi\u1ea3i ph\u00e1p n\u00e0y c\u00f3 ti\u1ec1m n\u0103ng l\u1edbn trong c\u00e1c \u1ee9ng d\u1ee5ng thu\u1ed9c l\u0129nh v\u1ef1c truy\u1ec1n th\u00f4ng v\u00e0 x\u1eed l\u00fd t\u00edn hi\u1ec7u s\u1ed1 (DSP) chuy\u00ean d\u1ee5ng.<\/p>","protected":false},"excerpt":{"rendered":"<p>Abstract This paper addresses the multi-frequency clock synthesis issue in Beidou Generation II RF chips, proposing a clock synthesis solution based on fractional frequency division technology. This solution can unify various external input clocks into the required 16.368 MHz system clock and is implemented using hardware description language (HDL). The design has been validated through [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":1300,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[30,31],"tags":[34],"class_list":["post-1301","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-industry-insights","category-blog","tag-gene-xu"],"acf":[],"_links":{"self":[{"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/posts\/1301","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/comments?post=1301"}],"version-history":[{"count":1,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/posts\/1301\/revisions"}],"predecessor-version":[{"id":1302,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/posts\/1301\/revisions\/1302"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/media\/1300"}],"wp:attachment":[{"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/media?parent=1301"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/categories?post=1301"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.wallisemi.com\/vi\/wp-json\/wp\/v2\/tags?post=1301"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}